In recent years, with the performance improvement of information processing apparatuses, the data rate of data signals transmitted and received inside and outside the apparatuses is being increased.
In a reception circuit, clock and data recovery (CDR), which reproduces data and a clock from a transmitted data signal, is carried out.
As one of methods of CDR, a method of interpolating a phase of a reference clock to generate sampling clocks, and reproducing data using the sampling clocks is provided. In this method, it becomes possible to make a phase adjustment with high precision using a reference clock having high precision. However, a clock source for generating a reference clock having high precision is used, and thus the cost and the circuit size are increased.
On the other hand, a method of performing data sampling using a clock reproduced from input data without using a reference clock, and outputting data with reduced jitter is provided. In this method, the phase difference and the frequency difference between a clock and input data is detected so that adjustment of the clock is carried out. Here, the phase of the clock is detected using a 2× sampling method, in which sampling is performed two times in one unit interval (UI). On the other hand, the frequency of the clock is detected using a 4× sampling method, in which sampling is performed four times in one UI.
In CDR not using a reference clock, if a frequency is detected by the 4× sampling method as described above, the area of a circuit that performs sampling becomes relatively large.
The following are reference documents.    [Document 1] Japanese Laid-open Patent Publication No. 2004-214825,    [Document 2] Japanese Laid-open Patent Publication No. 2004-153396 and    [Document 3] U.S. Pat. No. 6,055,286.